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PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1153 is a low-cost, full featured, synchronous voltage-mode controller designed for use in single ended power supply applications where efficiency is of primary concern. Synchronous operation allows for the elimination of heat sinks in many applications. The SC1153 is ideal for implementing DC/DC converters needed to power advanced microprocessors, such as Pentium(R) lll, in both single and multiple processor configurations. Internal level-shift, high-side drive circuitry, and preset shoot-thru control, allows for use of inexpensive n-channel power switches. SC1153 features include an integrated 5-bit VID DAC, temperature compensated voltage reference, triangle wave oscillator, current limit comparator, frequency shift over-current protection, and an accessible, internally compensated error amplifier. Power good signaling, logic compatible shutdown, and over voltage protection are also provided. The SC1153 operates at a fixed 200KHz, providing an optimum compromise between efficiency, external component size, and cost.
FEATURES *= Low cost / full featured *= Synchronous operation *= 5 Bit VID programmable output *= On-chip power good and OVP functions *= Designed to meet Intel VRM 8.4 (Pentium(R) IlI) *= 1.3V to 3.5V Range, 1% tolerance APPLICATIONS *= Pentium(R) IlI Core Supply *= Multiple Microprocessor Supplies *= Voltage Regulator Modules (VRM) *= Programmable Power Supplies *= High Efficiency DC/DC Conversion ORDERING INFORMATION
DEVICE
(1)
PACKAGE SO-20
TEMP. RANGE (TJ) 0 - 125C
SC1153CSW.TR
Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices.
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
1.25V REF
VCC CS-
CS+
SHUTDOWN BSTH CURRENT LIMIT UPPER FET LEVEL SHIFT AND DRIVE
70mV VID4 VID3 VID2 VID1 VID0 200kHz OSCILLATOR S D/A R Q
DH
PGNDH
VOSENSE OPEN COLLECTORS PWRGOOD VCC ERROR AMP SYNCHRONOUS FET DRIVE BSTL SHOOT-THRU CONTROL
DL
(20-Pin SOIC)
OVP PGNDL
GND
Pentium is a registered trademark of Intel Corporation
1
(c) 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VIN VCC to GND PGND to GND BST to GND Thermal Resistance JC Junction to Case Thermal Resistance JA Junction to Ambient Operating TA Temperature Range Storage TSTG Temperature Range Lead Temperature TLEAD (Soldering) 10 sec Maximum -0.3 to 7 1 -0.3 to 15 30 90 0 to 70 -65 to +150 300 Units V V V C/W C/W C C C
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC PARAMETER Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Gain (AOL) Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle DH Sink/Source Current DL Sink/Source Current OVP Threshold Voltage OVP Source Current Power Good Threshold Voltage Dead Time NOTE: (1) Specification refers to application circuit (Figure 1.). (2) This part is ESD sensitive. Use of standard ESD handling precautions is required. VOVP = 3V 10 90 50 100 110 BSTH - DH = 4.5V, DH - PGNDH = 2V BSTL - DL = 4.5V, DL - PGNDL = 2V IO = 2A VCC VCC = 5.0 IO = 0.3A to 15A(1) All VID codes VOSENSE to VO 60 180 90 1 1 120
(1) (1)
CONDITIONS
MIN
TYP
MAX
UNITS
See Output Voltage Table. 4.2 5 1 0.5 35 70 200 95 80 220 7 V mA % % dB mV kHz % A A % mA % ns
2 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. Pin Name GND VCC OVP PWRGOOD CS(-) CS(+) PGNDH DH NC PGNDL DL BSTL BSTH SHUTDOWN VOSENSE VID4 VID3
(1) (1) (1) (1)
Pin Function Small Signal Analog and Digital Ground Chip Supply Voltage High Signal Out if VO > Setpoint + 20% Open collector logic output, high if VO within 10% of setpoint Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Not Connected Power Ground for Low Side Switch Low Side Driver Output Vcc for Low Side Driver (Boost) Vcc for High Side Driver (Boost) Logic Low shuts down the converter Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB)
VID2(1) VID1 VID0
(1) (1)
PIN CONFIGURATION
3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
APPLICATION CIRCUIT
Q1 5V IN 4 uH + C3 1000uF C1 0.1uF + C2 1000uF C4 1000uF R2 10k + R5 10 + Q2 D1 1N5817 + + + + + L1 R1 5mOhm C6 1000uF C8 1000uF C10 1000uF
VCCP
C5 1000uF
C7 1000uF
C9 1000uF
C12 0.1uF
12V IN R4 U1 2 OVP VID0 VID1 VID2 VID3 VID4 3 20 19 18 17 14 1 10 C13 0.1uF 9 VCC OVP VID0 VID1 VID2 VID3 SHUTDOWN GND PGNDL NC SC1153CS CS+ CSVOSENSE PWRGOOD VID4 BSTH DH PGNDH DL BSTL 6 5 15 4 16 13 8 7 11 12 C11 0.1uF 1.00k R3 2.32k
SHUTDOWN PWRGOOD
Pentium ll Power Supply Figure 1.
(R)
MATERIALS LIST
Quantity 4 9 1 1 2 1 1 1 1 1 1 Reference Part/Description Vendor Various SANYO Various 8 Turns 16AWG on MICROMETALS T50-52D core See notes IRC Various Various Various Various SEMTECH FET selection requires trade-off between efficiency and cost. Absolute maximum RDS(ON) = 22 m OAR-1 Series MV-GX or equiv. Low ESR Notes C1,C11-C13 0.1F Ceramic C2-C10 D1 L1 Q1, Q2 R1 R2 R3 R4 R5 U1 1000F/6.3V 1N5817 4H See notes 5m 10k, 5%, 1/8W 2.32k, 1%, 1/8W 1k, 1%, 1/8W 10, 5%, 1/8W SC1153CS
4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
OUTPUT VOLTAGE TABLE
Unless specified: VCC = 5.00V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25C PARAMETER Output Voltage CONDITIONS IO = 2A in Application Circuit (Figure 1) VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 MIN 1.287 1.336 1.386 1.435 1.485 1.534 1.584 1.633 1.683 1.732 1.782 1.832 1.881 1.931 1.980 2.030 1.980 2.079 2.178 2.277 2.376 2.475 2.574 2.673 2.772 2.871 2.970 3.069 3.168 3.267 3.366 3.465 TYP 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 MAX 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 1.868 1.919 1.969 2.020 2.070 2.020 2.121 2.222 2.323 2.424 2.525 2.626 2.727 2.828 2.929 3.030 3.131 3.232 3.333 3.434 3.535 UNITS V
5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
CHARACTERISTIC CURVES
SC1153 Efficiency in Application Circuit (Figure 1).
100%
95%
90% Efficiency Vo=3.5V 85% 3.0V 2.5V 1.8V 75% 2.0V
80%
70% 0 2 4 6 8 10 Output Current (Amps) 12 14 16
SC1153 Regulation in Application Circuit (Figure 1).
0
-5
Vout (mV)
-10
-15
-20
-25 0 2 4 6 8 10 Output Current (Amps) 12 14 16
6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS
PRELIMINARY - October 3, 2000
SC1153
OUTLINE DRAWING SO-20
Ref. MS-013AC
THEORY OF OPERATION
The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200kHz. The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals are modified by the "shoot-through control" circuitry so that the top FET turn-on is delayed until the bottom FET has turned off, and visa-versa. The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an overcurrent condition. The latch is reset at the start of each oscillator period. The PWRGOOD and OVP signals are derived from the voltage at the VOSENSE pin by comparators fed from the internal feedback chain.
ECN00-1346 7 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

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